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Hardik
- Rate €4
- Response 1h
-
Students3
Number of students Hardik has accompanied since arriving at Superprof
Number of students Hardik has accompanied since arriving at Superprof
€4/h
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- Professional Coaching
Learn ASIC Verification from Experienced Verification Engineer from Industry, with sound Knowledge and skills of UVM, System Verilog, Verilog, Linux and Perl
- Professional Coaching
Lesson location
About Hardik
I am an ASIC Verification Engineer with 1.5 years of professional experience.
I am having experience of Verifying Complex System on Chip with Processor and various IPs. I used to write different test-cases for SoC Connectivity, Register Access, Glue Logic Verification etc. for different System on chips (SoC).
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About the lesson
- Primary School
- Secondary School
- Post-Secondary Education
- +14
levels :
Primary School
Secondary School
Post-Secondary Education
1st year of Sixth Form
2nd year of Sixth Form
Adult education
Bachelor
Masters
Doctorate
Other
Qualified Lawyer Transfer Scheme
MBA
Kindergarten
Beginner
Intermediate
Advanced
Kids
- English
All languages in which the lesson is available :
English
Apart from Industrial Experience, I am also having teaching Experience at university level which helps me to deliver the sessions with ease and lucid manner.
I usually deliver the sessions for following topics.
Linux (basic commands,directory structure, use of grep, sed, awk etc.)
Perl Scripting (basics of Perl, How to Develop Automatic Testcases using Perl Scripts)
Verilog (Verilog HDL code development starting for small RTLs than growing gradually to big RTLs, FSMs, FIFO, Arbiter, Traffic Light Controllers, AMBA AHB bus protocol)
System Verilog (Basic Data Structures like, Array, queue, associative array, Basic Data types like reg, wire, logic,Basics of OOPs concepts like parent class,child class, polymorphism,Inheritance,Encapsulation, Abstract class, Randomization, coverage, Environment Building which includes creation and proper connection of Agent, scoreboard, DUT, Interfaces etc., writing assertions)
UVM (Basic structure of UVM,Components vs objects, Phases,Factory registration,Verbosity,Interfaces, Conffig DB, Resource DB)
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Rates
Rate
- €4
Pack rates
- 5 h: €20
- 10 h: €40
online
- €4/h
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